阮爱武
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研究员
硕士生导师
- 性别：女
- 毕业院校：西北工业大学
- 学历：博士研究生毕业
- 学位：工学博士学位
- 在职信息：在职人员
- 所在单位：集成电路科学与工程学院（示范性微电子学院）
- 办公地点：211楼507
- 联系方式：269ac96604140686dcfa10d8fa9b2497fa9ba35d425f67c2ab81b0748f4f93def17a179e463ffaaefbfcaa3c8325c8fd06f3c1ead9de45466883262e6b69830557a5be840b26576d0191d2a54dec53f92ba9fe6a4d3457c7c5d45f123e1a5adc7bba48afec3adf45d89dc55a60505dd33768a81fdb5e04af3489b83bd72cf5cc
- 电子邮箱：622226f3c5ee2eaa2d7850a062289a24c48720a8d57d8463d4668a72a9ee1900d5e3b0cc99e931dff0ec18f98d14eadacb92daa2344a62ee564264fbea255f0e769c93d320a4128937cf41b2aae24e76616ceba6373ea9c6a5a2c6249b77e4ef4269defaf62b7e7c267b09ffc2c32d16ec5e7fd4743a6cf704b47fd098a5e79c
访问量：
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[1]
et al
and A.W. Ruan,
A Stream-Mode Based HW/SW Co-Emulation System for SOC Test and Verification
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[2]
et al
and A.W. Ruan,
A Parasitic Effect – Free Test Scheme for Ferroelectric Random Access Memory (FRAM)
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[3]
et al
and A.W. Ruan,
A Self-Defined Communication Protocol of Transport Layer in Hierarchy Transaction – Level Architecture for SOC Verification
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[4]
et al
and A.W. Ruan,
Adjustable Gain CTIA Cell with Variable Integration Time for IRFPA Applications
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[5]
et al
and A.W. Ruan,
An ALU-Based Universal Architecture for FIR Filters
-
[6]
et al
and A.W. Ruan,
Automatic Configuration Generation for A SOC Co-Verification Technology Based FPGA Functional Test System
-
[7]
et al
and A.W. Ruan,
An Automatic Test Approach for Field Programmable Gate Array (FPGA)
-
[8]
et al,
A.W. Ruan,
and X. Cheng,
A Run-Time RTL Debugging Methodology for FPGA-based Co-Simulation
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[9]
et al,
Aiwu Ruan,
and Haocheng Huang,
A New Event Driven Testbench Synthesis Engine for FPGA Emulation
-
[10]
et al,
Aiwu Ruan,
and Haocheng Huang,
A New Event Driven Testbench Synthesis Engine for FPGA Emulation
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[11]
et al
and A.W. Ruan,
Debugging Methodology for A Synthesizable Testbench FPGA Emulator
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[12]
B. Hu,
A.W. Ruan,
and K. Shen,
Design of A Control Circuit for A User Reconfigurable ROIC for IRFPA Applications
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[13]
et al
and A.W. Ruan,
Performance Estimation for A EDA Tool Based HW/SW Co-Verification Environment
-
[14]
阮爱武
项传银，
基于故障映射的FPGA互连资源故障测试与定位
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[15]
et al
and A.W. Ruan,
Graph Theory for FPGA Minimum Configurations
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[16]
et al
and A.W. Ruan,
SOC HW/SW Co-Verification Based Debugging Technique
-
[17]
et al
and Aiwu Ruan,
A Built-In Self-Test (BIST) System with Non-Intrusive TPG and ORA for FPGA Test and Diagnosis
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[18]
et al
and Aiwu Ruan,
Insight into a Generic Interconnect Resource Model for Xilinx Virtex and Spartan Series FPGAs
-
[19]
et al
and Aiwu Ruan,
A bitstream readback-based automatic functional test and diagnosis
-
[20]
A.W. Ruan,
SOC HW/SW Co-Verification Technology for Application of FPGA Test and Diagnosis
